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cy7c1461av33 cy7c1463av33 36-mbit (1 m 36/2 m 18) flow-through sram with nobl? architecture cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-05356 rev. *l revised july 24, 2012 36-mbit (1 m 36/2 m 18) flow-through sram with nobl? architecture features no bus latency? (nobl?) arch itecture eliminates dead cycles between write and read cycles supports up to 133 mhz bus operations with zero wait states ? data is transferred on every clock pin compatible and functionally equivalent to zbt? devices internally self timed output buf fer control to eliminate the need to use oe registered inputs for flow through operation byte write capability 3.3 v and 2.5 v i/o power supply fast clock-to-output times ? 6.5 ns (for 133 mhz device) clock enable (cen ) pin to enable clock and suspend operation synchronous self timed writes asynchronous output enable cy7c1461av33, cy7c1463av33 available in jedec-standard pb-free 100-pin tqfp package. three chip enables for simple depth expansion automatic power down feature available using zz mode or ce deselect burst capability ? linear or interleaved burst order low standby power functional description the cy7c1461av33/cy7c1463av33 are 3.3 v, 1 m 36/2 m 18 synchronous flow-through burst srams designed specifically to support unlimited true back-to-back read and write operations without the insertion of wait states. the cy7c1461av33/cy7c1463av33 is equipped with the advanced nobl logic required to enable consecutive read and write operations with data being transferred on every clock cycle. this feature dramatically improves th e throughput of data through the sram, especially in systems t hat require frequent write-read transitions. all synchronous inputs pass through input registers controlled by the rising edge of the clock. the clock input is qualified by the clock enable (cen ) signal, which when deasserted suspends operation and extends the previous clock cycle. maximum access delay from the clock rise is 6.5 ns (133 mhz device). write operations are controlled by the two or four byte write select (bw x ) and a write enable (we ) input. all writes are conducted with on-chip synchronous self timed write circuitry. three synchronous chip enables (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) provide for easy bank selection and output tri-state c ontrol. to avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence. selection guide description 133 mhz unit maximum access time 6.5 ns maximum operating current 310 ma maximum cmos standby current 120 ma
cy7c1461av33 cy7c1463av33 document number: 38-05356 rev. *l page 2 of 24 logic block diagram ? cy7c1461av33 c mode bw a bw b we ce1 ce2 ce3 oe read logic dqs dqp a dqp b dqp c dqp d memory array e input register bw c bw d address register write registry and data coherency control logic burst logic a0' a1' d1 d0 q1 q0 a0 a1 adv/ld ce adv/ld c clk cen write drivers d a t a s t e e r i n g s e n s e a m p s write address register a0, a1, a o u t p u t b u f f e r s e zz sleep control
cy7c1461av33 cy7c1463av33 document number: 38-05356 rev. *l page 3 of 24 logic block diagram ? cy7c1463av33 c mode bw a bw b we ce1 ce2 ce3 oe read logic dqs dqp a dqp b memory array e input register address register write registry and data coherency control logic burst logic a0' a1' d1 d0 q1 q0 a0 a1 adv/ld ce adv/ld c c lk c en write drivers d a t a s t e e r i n g s e n s e a m p s write address register a0, a1, a o u t p u t b u f f e r s e zz sleep control
cy7c1461av33 cy7c1463av33 document number: 38-05356 rev. *l page 4 of 24 contents pin configurations ........................................................... 5 pin definitions .................................................................. 7 functional overview ........................................................ 8 single read accesses ................................................ 8 burst read accesses .................................................. 8 single write accesses ................................................. 8 burst write accesses .................................................. 9 sleep mode ................................................................. 9 interleaved burst address tabl e ................................. 9 linear burst address table ......................................... 9 zz mode electrical characteri stics .............................. 9 truth table ...................................................................... 10 truth table for read/write ............................................ 11 truth table for read/write ............................................ 11 maximum ratings ........................................................... 12 operating range ............................................................. 12 electrical characteristics ............................................... 12 capacitance .................................................................... 13 thermal resistance ........................................................ 13 ac test loads and waveforms ..................................... 13 switching characteristics .............................................. 14 switching waveforms .................................................... 15 ordering information ...................................................... 18 ordering code definitions ..... .................................... 18 package diagrams .......................................................... 19 acronyms ........................................................................ 20 document conventions ................................................. 20 units of measure ....................................................... 20 document history page ................................................. 21 sales, solutions, and legal information ...................... 24 worldwide sales and design s upport ......... .............. 24 products .................................................................... 24 psoc solutions ......................................................... 24
cy7c1461av33 cy7c1463av33 document number: 38-05356 rev. *l page 5 of 24 pin configurations figure 1. 100-pin tqfp (14 20 1.4 mm) pinout a a a a a1 a0 nc/288m nc/144m v ss v dd a a a a a a dqp b dq b dq b v ddq v ss dq b dq b dq b dq b v ss v ddq dq b dq b v ss nc v dd dq a dq a v ddq v ss dq a dq a dq a dq a v ss v ddq dq a dq a dqp a dqp c dq c dq c v ddq v ss dq c dq c dq c dq c v ss v ddq dq c dq c nc v dd nc v ss dq d dq d v ddq v ss dq d dq d dq d dq d v ss v ddq dq d dq d dqp d a a ce 1 ce 2 bw d bw c bw b bw a ce 3 v dd v ss clk we cen oe a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a a adv/ld zz mode nc/72m cy7c1461av33 byte a byte b byte d byte c a a
cy7c1461av33 cy7c1463av33 document number: 38-05356 rev. *l page 6 of 24 figure 2. 100-pin tqfp (14 20 1.4 mm) pinout pin configurations (continued) a a a a a1 a0 nc/288m nc/144m v ss v dd a a a a a a a nc nc v ddq v ss nc dqp a dq a dq a v ss v ddq dq a dq a v ss nc v dd dq a dq a v ddq v ss dq a dq a nc nc v ss v ddq nc nc nc nc nc nc v ddq v ss nc nc dq b dq b v ss v ddq dq b dq b nc v dd nc v ss dq b dq b v ddq v ss dq b dq b dqp b nc v ss v ddq nc nc nc a a ce 1 ce 2 nc nc bw b bw a ce 3 v dd v ss clk we cen oe a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a a adv/ld zz mode nc/72m cy7c1463av33 byte a byte b a a
cy7c1461av33 cy7c1463av33 document number: 38-05356 rev. *l page 7 of 24 pin definitions pin name i/o description a 0 , a 1 , a input- synchronous address inputs. used to select one of the address locations. sampled at the rising edge of the clk. a [1:0] are fed to the two-bit burst counter. bw a , bw b , bw c , bw d input- synchronous byte write inputs, active low . qualified with we to conduct writes to the sram. sampled on the rising edge of clk. we input- synchronous write enable input, active low . sampled on the rising edge of clk if cen is active low. this signal must be asserted low to initiate a write sequence. adv/ld input- synchronous advance or load input . used to advance the on-chip address counter or load a new address. when high (and cen is asserted low) the internal burst co unter is advanced. when low, a new address can be loaded into the device for an access. after deselecting, drive adv/ld low to load a new address. clk input- clock clock input . used to capture all synchronous inputs to the device. clk is qualified with cen . clk is only recognized if cen is active low. ce 1 input- synchronous chip enable 1 input, active low . sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 to select or deselect the device. ce 2 input- synchronous chip enable 2 input, active high . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 to select or deselect the device. ce 3 input- synchronous chip enable 3 input, active low . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select or dese lect the device. oe input- asynchronous output enable, asynchronous input, active low . combined with the synchronous logic block inside the device to control the direction of the i/o pins . when low, the i/o pins are allowed to behave as outputs. when deasserted high, i/o pins are tri-stated and act as input data pins. oe is masked during the data portion of a write sequence, during the firs t clock when emerging from a deselected state, and when the device is deselected. cen input- synchronous clock enable input, active low . when asserted low the clock signal is recognized by the sram. when deasserted high the clock signal is masked. because deasserting cen does not deselect the device, use cen to extend the previo us cycle when required. zz input- asynchronous zz ?sleep? input . this active high input places the device in a non time critical sleep condition with data integrity preserved. during normal operation, this pin has to be low or left floating. zz pin has an internal pull down. dq s i/o- synchronous bidirectional data i/o lines . as inputs, they feed into an on-chip data register that is triggered by the rising edge of clk. as outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. the di rection of the pins is controlled by oe . when oe is asserted low, the pins beh ave as outputs. when high, dq s and dqp [a:d] are placed in a tri-state condition.the outputs ar e automatically tri-stated during the data portion of a write sequence, during the first clock when emer ging from a deselected state, and when the device is deselected, regardless of the state of oe . dqp x i/o- synchronous bidirectional data parity i/o lines. functionally, these signals are identical to dq s . during write sequences, dqp x is controlled by bw x correspondingly. mode input strap pin mode input. selects the burst order of the device. when tied to gnd selects linear burst sequence. when tied to v dd or left floating selects interleaved burst sequence. v dd power supply power supply inputs to the core of the device . v ddq i/o power supply power supply for i/o circuitry . v ss ground ground for the device . nc n/a no connects . not internally connected to the die. nc/72m n/a not connected to the die . can be tied to any voltage level.
cy7c1461av33 cy7c1463av33 document number: 38-05356 rev. *l page 8 of 24 functional overview the cy7c1461av33/cy7c1463av33 is a synchronous flow through burst sram designed s pecifically to eliminate wait states during write-read transitions. all synchronous inputs pass through input registers controlled by the rising edge of the clock. the clock signal is qualified with the clock enable input signal (cen ). if cen is high, the clock signal is not recognized and all internal states are maintained. all synchronous operations are qualified with cen . maximum access delay from the clock rise (t cdv ) is 6.5 ns (133 mhz device). accesses can be initiated by asserting all three chip enables (ce 1 , ce 2 , ce 3 ) active at the rising edg e of the clock. if cen is active low and adv/ld is asserted low, the address presented to the device is latched. the access can either be a read or write operation, depend ing on the status of the write enable (we ). bw x can be used to conduct byte write operations. write operations are qualif ied by the write enable (we ). all writes are simplified with on-chip synchronous self timed write circuitry. three synchronous chip enables (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) simplify depth expansion. all operations (reads, writes, and de selects) are pipelined. adv/ld must be driven low after the dev ice is deselected to load a new address for the next operation. single read accesses a read access is initiated when these conditions are satisfied at clock rise: cen is asserted low ce 1 , ce 2 , and ce 3 are all asserted active the write enable input signal we is deasserted high adv/ld is asserted low the address presented to the address inputs is latched into the address register and presented to the memory array and control logic. the control logic determines that a read access is in progress and allows the requested data to propagate to the output buffers. the data is available within 6.5 ns (133 mhz device) provided oe is active low. after the first clock of the read access, the output buffers are controlled by oe and the internal control logic. oe must be driven low for the device to drive out the requested data. on the subsequent clock, another operation (read/write/deselect) can be initiated. when the sram is deselected at clock rise by one of the chip enable signals, its output is tri-stated immediately. burst read accesses the cy7c1461av33/cy7c1463av33 has an on-chip burst counter that provides the ability to supply a single address and conduct up to four reads without reasserting the address inputs. adv/ld must be driven low to load a new address into the sram, as described in the single read accesses section. the sequence of the burst counter is determined by the mode input signal. a low input on mode selects a linear burst mode, a high selects an interleaved burst sequence. both burst counters use a0 and a1 in t he burst sequence, and wraps around when incremented sufficiently. a high input on adv/ld increments the internal burst count er regardless of the state of chip enable inputs or we . we is latched at the beginning of a burst cycle. therefore, the type of access (read or write) is maintained throughout the burst sequence. single write accesses write access are initiated when the following conditions are satisfied at clock rise: (1) cen is asserted low, (2) ce 1 , ce 2 , and ce 3 are all asserted active, and (3) the write signal we is asserted low. the address pr esented to the address bus is loaded into the address register. the write signals are latched into the control logic block. the data lines are automatically tri-stated regardless of the state of the oe input signal. this allows the external logic to present the data on dqs and dqp x . on the next clock rise the data presented to dqs and dqp x (or a subset for byte write operations, see truth table for details) inputs is latched into the device and the write is complete. additional accesses (read/write/deselect) can be initiated on this cycle. the data written during the writ e operation is controlled by bw x signals. the cy7c1461av33/cy7c1463av33 provides byte write capability that is described in the truth table. asserting the (we ) with the selected byte write select input selectively writes to only the desired bytes. bytes not selected during a byte write operation remains unaltered. a synchronous self timed write mechanism is provided to simp lify the write operations. byte write capability is included to greatly simplify read/modify/write sequences, which can be reduced to simple byte write operations. because the cy7c1461av33/cy7c1463av33 is a common i/o device, data must not be driven into the device when the outputs are active. the oe can be deasserted high before presenting data to the dqs and dqp x inputs. this tri-states the output drivers. as a safety precaution, dqs and dqp x are automatically tri-stated during the data porti on of a write cycle, regardless of the state of oe . nc /144m n/a not connected to the die . can be tied to any voltage level. nc /288m n/a not connected to the die . can be tied to any voltage level. nc /576m n/a not connected to the die . can be tied to any voltage level. nc /1g n/a not connected to the die . can be tied to any voltage level. pin definitions (continued) pin name i/o description
cy7c1461av33 cy7c1463av33 document number: 38-05356 rev. *l page 9 of 24 burst write accesses the cy7c1461av33/cy7c1463av33 has an on-chip burst counter that provides the ability to supply a single address and conduct up to four write operations without reasserting the address inputs. adv/ld must be driven low to load the initial address, as described in the single write accesses section. when adv/ld is driven high on the subsequent clock rise, the chip enables (ce 1 , ce 2 , and ce 3 ) and we inputs are ignored and the burst counter is incremented. the correct bw x inputs must be driven in each cycle of th e burst write, to write the correct bytes of data. sleep mode the zz input pin is an asynchronous input. asserting zz places the sram in a power conserva tion sleep mode. two clock cycles are required to enter into or exit from this sleep mode. when in this mode, data integrity is guaranteed. accesses pending when entering the sleep mode are not considered valid nor is the completion of the operation guaranteed. the device must be deselected prior to entering the sleep mode. ce 1 , ce 2 , and ce 3 , must remain inactive for the duration of t zzrec after the zz input returns low. interleaved burst address table (mode = floating or v dd ) first address a1:a0 second address a1:a0 third address a1:a0 fourth address a1:a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd) first address a1:a0 second address a1:a0 third address a1:a0 fourth address a1:a0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 zz mode electrical characteristics parameter description test conditions min max unit i ddzz sleep mode standby current zz > v dd ? ? 0.2 v ? 100 ma t zzs device operation to zz zz > v dd ? 0.2 v ? 2t cyc ns t zzrec zz recovery time zz < 0.2 v 2t cyc ?ns t zzi zz active to sleep current t his parameter is sampled ? 2t cyc ns t rzzi zz inactive to exit sleep curre nt this parameter is sampled 0 ? ns
cy7c1461av33 cy7c1463av33 document number: 38-05356 rev. *l page 10 of 24 truth table the truth table for cy7c1461av33/cy7c1463av33 follows. operation [1, 2, 3, 4, 5, 6, 7] address used ce 1 ce 2 ce 3 zz adv/ld we bw x oe cen clk dq deselect cycle none h x x l l x x x l l->h tristate deselect cycle none x x h l l x x x l l->h tristate deselect cycle none x l x l l x x x l l->h tristate continue deselect cycle none x x x l h x x x l l->h tristate read cycle (begin burst) extern al l h l l l h x l l l->h data out (q) read cycle (continue burst) next x x x l h x x l l l->h data out (q) nop/dummy read (begin burst) external l h l l l h x h l l->h tristate dummy read (continue burst) next x x x l h x x h l l->h tristate write cycle (begin burst) external l h l l l l l x l l->h data in (d) write cycle (continue burst) next x x x l h x l x l l->h data in (d) nop/write abort (begin burst) none l h l l l l h x l l->h tristate write abort (continue burst) next x x x l h x h x l l->h tristate ignore clock edge (stall) current x x x l x x x x h l->h ? sleep mode none x x x h x x x x x x tristate notes 1. x = ?don't care.? h = logic high, l = logic low. bw x = l signifies at least one byte write select is active, bw x = valid signifies that the desired byte write selects are asserted, see truth table for details. 2. write is defined by bw x , and we . see truth table for read or write. 3. when a write cycle is detected, all ios are tristated, even during byte writes. 4. the dqs and dqp x pins are controlled by the current cycle and the oe signal. oe is asynchronous and is not sampled with the clock. 5. cen = h, inserts wait states. 6. device powers up deselected and the ios in a tri-state condition, regardless of oe . 7. oe is asynchronous and is not sampled with the clock rise. it is masked internally during write cycles. during a read cycle dqs a nd dqp x = tri-state when oe is inactive or when the device is deselected, and dqs and dqp x = data when oe is active.
cy7c1461av33 cy7c1463av33 document number: 38-05356 rev. *l page 11 of 24 truth table for read/write function (cy7c1461av33) [8, 9] we bw a bw b bw c bw d read h x x x x write ? no bytes written l h h h h write byte a ? (dq a and dqp a )llhhh write byte b ? (dq b and dqp b )lhlhh write byte c ? (dq c and dqp c )lhhlh write byte d ? (dq d and dqp d )lhhhl write all bytes l l l l l truth table for read/write function (cy7c1463av33) [8, 9] we bw b bw a read h x x write ? no bytes written l h h write byte a ? (dq a and dqp a )lhl write byte b ? (dq b and dqp b )llh write both bytes l l l notes 8. x = ?don't care.? h = logic high, l = logic low. bw x = l signifies at least one byte write select is active, bw x = valid signifies that the desired byte write selects are asserted, see truth table for details. 9. table only lists a partial listing of the by te write combinations. any combination of bw x is valid. appropriate write is done based on which byte write is active.
cy7c1461av33 cy7c1463av33 document number: 38-05356 rev. *l page 12 of 24 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature .... ............ ............... ?65 ? c to +150 ? c ambient temperature with power applied ... .............. .............. .......... ?55 ? c to +125 ? c supply voltage on v dd relative to gnd .....?0.5 v to +4.6 v supply voltage on v ddq relative to gnd .... ?0.5 v to +v dd dc voltage applied to outputs in tri-state ........................................?0.5 v to v ddq + 0.5 v dc input voltage ................................ ?0.5 v to v dd + 0.5 v current into outputs (low) .... .................................... 20 ma static discharge voltage (mil-std-883, method 3015) ................................ > 2001 v latch up current .................................................. > 200 ma operating range range ambient temperature v dd v ddq commercial 0 c to +70 c 3.3 v ? ? 5% / + 10% 2.5 v ? 5% to v dd industrial ?40 c to +85 c electrical characteristics over the operating range parameter [10, 11] description test conditions min max unit v dd power supply voltage 3.135 3.6 v v ddq i/o supply voltage for 3.3 v i/o 3.135 v dd v for 2.5 v i/o 2.375 2.625 v v oh output high voltage for 3.3 v i/o, i oh = ?4.0 ma 2.4 ? v for 2.5 v i/o, i oh = ?1.0 ma 2.0 ? v v ol output low voltage for 3.3 v i/o, i ol = 8.0 ma ? 0.4 v for 2.5 v i/o, i ol = 1.0 ma ? 0.4 v v ih input high voltage [10] for 3.3 v i/o 2.0 v dd + 0.3 v v for 2.5 v i/o 1.7 v dd + 0.3 v v v il input low voltage [10] for 3.3 v i/o ?0.3 0.8 v for 2.5 v i/o ?0.3 0.7 v i x input leakage current except zz and mode gnd ? v i ? v ddq ?5 5 ? a input current of mode input = v ss ?30 ? ? a input = v dd ?5 ? a input current of zz input = v ss ?5 ? ? a input = v dd ?30 ? a i oz output leakage current gnd ? v i ? v ddq, output disabled ?5 5 ? a i dd v dd operating supply current v dd = max, i out = 0 ma, f = f max = 1/t cyc 7.5 ns cycle, 133 mhz ?310ma i sb1 automatic ce power down current ? ttl inputs v dd = max, device deselected, v in ? v ih or v in ? v il ; f = f max , inputs switching 7.5 ns cycle, 133 mhz ?180ma i sb2 automatic ce power down current ? cmos inputs v dd = max, device deselected, v in ?? 0.3 v or v in > v dd ? 0.3 v, f = 0, inputs static 7.5 ns cycle, 133 mhz ?120ma i sb3 automatic ce power down current ? cmos inputs v dd = max, device deselected, v in ? 0.3 v or v in > v ddq ? 0.3 v f = f max , inputs switching 7.5 ns cycle, 133 mhz ?180ma i sb4 automatic ce power down current ? ttl inputs v dd = max, device deselected, v in ? v dd ? 0.3 v or v in ? 0.3 v, f = 0, inputs static 7.5 ns cycle, 133 mhz ?135ma notes 10. overshoot: v ih(ac) < v dd + 1.5 v (pulse width less than t cyc /2), undershoot: v il(ac) > ?2 v (pulse width less than t cyc /2). 11. t power-up : assumes a linear ramp from 0 v to v dd(min) within 200 ms. during this time v ih < v dd and v ddq < v dd .
cy7c1461av33 cy7c1463av33 document number: 38-05356 rev. *l page 13 of 24 capacitance parameter [12] description test conditions 100-pin tqfp max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v dd = 3.3 v, v ddq = 2.5 v 6.5 pf c clk clock input capacitance 3 pf c io input/output capacitance 5.5 pf thermal resistance parameter [12] description test conditions 100-pin tqfp package unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, according to eia/jesd51. 25.21 c/w ? jc thermal resistance (junction to case) 2.28 c/w ac test loads and waveforms figure 3. ac test loads and waveforms output r = 317 ? r = 351 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.5 v 3.3 v all input pulses v ddq gnd 90% 10% 90% 10% ? 1ns ? 1ns (c) output r = 1667 ? r = 1538 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.25 v 2.5 v all input pulses v ddq gnd 90% 10% 90% 10% ? 1ns ? 1ns (c) 3.3 v i/o test load 2.5 v i/o test load note 12. tested initially and after any design or proc ess change that may affect these parameters.
cy7c1461av33 cy7c1463av33 document number: 38-05356 rev. *l page 14 of 24 switching characteristics over the operating range parameter [13, 14] description 133 mhz unit min max t power [15] 1 ? ms clock t cyc clock cycle time 7.5 ? ns t ch clock high 2.5 ? ns t cl clock low 2.5 ? ns output times t cdv data output valid after clk rise ? 6.5 ns t doh data output hold after clk rise 2.5 ? ns t clz clock to low z [16, 17, 18] 2.5 ? ns t chz clock to high z [16, 17, 18] ? 3.8 ns t oev oe low to output valid ? 3.0 ns t oelz oe low to output low z [16, 17, 18] 0 ? ns t oehz oe high to output high z [16, 17, 18] ? 3.0 ns setup times t as address setup before clk rise 1.5 ? ns t als adv/ld setup before clk rise 1.5 ? ns t wes we , bw x setup before clk rise 1.5 ? ns t cens cen setup before clk rise 1.5 ? ns t ds data input setup before clk rise 1.5 ? ns t ces chip enable setup before clk rise 1.5 ? ns hold times t ah address hold after clk rise 0.5 ? ns t alh adv/ld hold after clk rise 0.5 ? ns t weh we , bw x hold after clk rise 0.5 ? ns t cenh cen hold after clk rise 0.5 ? ns t dh data input hold after clk rise 0.5 ? ns t ceh chip enable hold after clk rise 0.5 ? ns notes 13. timing reference level is 1.5 v when v ddq = 3.3 v and is 1.25 v when v ddq = 2.5 v. 14. test conditions shown in (a) of figure 3 on page 13 unless otherwise noted. 15. this part has a voltage regulator internally; t power is the time that the power needs to be supplied above v dd(minimum) initially, before a read or write operation can be initiated. 16. t chz , t clz ,t oelz , and t oehz are specified with ac test co nditions shown in part (b) of figure 3 on page 13 . transition is measured 200 mv from steady-state voltage. 17. at any voltage and temperature, t oehz is less than t oelz and t chz is less than t clz to eliminate bus contention between srams when sharing the same data bus. these specifications do not imply a bus c ontention condition, but reflect parameters guaranteed over worst case user conditions . device is designed to achieve high z prior to low z under the same system conditions. 18. this parameter is sampled and not 100% tested.
cy7c1461av33 cy7c1463av33 document number: 38-05356 rev. *l page 15 of 24 switching waveforms figure 4. read/write waveforms [19, 20, 21] write d(a1) 123 456789 clk t cyc t cl t ch 10 ce t ceh t ces we cen t cenh t cens bw x adv/ld t ah t as address a1 a2 a3 a4 a5 a6 a7 t dh t ds dq c ommand t clz d(a1) d(a2) q(a4) q(a3) d(a2+1) t doh t chz t cdv write d(a2) burst write d(a2+1) read q(a3) read q(a4) burst read q(a4+1) write d(a5) read q(a6) write d(a7) deselect oe t oev t oelz t oehz dont care undefined d(a5) t doh q(a4+1) d(a7) q(a6) notes 19. for this waveform zz is tied low. 20. when ce is low, ce 1 is low, ce 2 is high and ce 3 is low. when ce is high, ce 1 is high or ce 2 is low or ce 3 is high. 21. order of the burst sequence is determined by the status of the mode (0 = linear, 1 = interleaved). burst operations are opti onal.
cy7c1461av33 cy7c1463av33 document number: 38-05356 rev. *l page 16 of 24 figure 5. nop, stall, and deselect cycles [22, 23, 24] switching waveforms (continued) read q(a3) 456 78910 a3 a4 a5 d(a4) 123 clk ce we cen bw [a:d] adv/ld address dq c ommand write d(a4) stall write d(a1) read q(a2) stall nop read q(a5) deselect continue deselect dont care undefined t chz a1 a2 q(a2) d(a1) q(a3) t doh q(a5) notes 22. for this waveform zz is tied low. 23. when ce is low, ce 1 is low, ce 2 is high and ce 3 is low. when ce is high, ce 1 is high or ce 2 is low or ce 3 is high. 24. the ignore clock edge or stall cycle (clock 3) illustrates cen being used to create a pause. a writ e is not performed during this cycle.
cy7c1461av33 cy7c1463av33 document number: 38-05356 rev. *l page 17 of 24 figure 6. zz mode timing [25, 26] switching waveforms (continued) t zz i supply clk zz t zzrec a ll inputs (except zz) dont care i ddzz t zzi t rzzi outputs (q) high-z deselect or read only notes 25. device must be deselected when entering zz mode. see truth t able for all possible signal conditions to deselect the device. 26. dqs are in high z when exiting zz sleep mode.
cy7c1461av33 cy7c1463av33 document number: 38-05356 rev. *l page 18 of 24 ordering code definitions ordering information cypress offers other versions of this type of product in different co nfigurations and features. the following table contains on ly the list of parts that are currently available. for a complete listing of all options, visit the cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products , or contact your loca l sales representative. cypress maintains a worldwide network of offices, solution cent ers, manufacturer?s representat ives and distributors. to find th e office closest to you, visit us at http://www.cypress.com /go/datasheet/offices . speed (mhz) ordering code package diagram part and package type operating range 133 CY7C1461AV33-133AXC 51-85050 100-pin tqfp (14 20 1.4 mm) pb-free commercial cy7c1463av33-133axc cy7c1461av33-133axi 51-85050 100-pin tqfp (14 20 1.4 mm) pb-free lndustrial temperature range: x = c or i c = commercial; i = industrial x = pb-free; x absent = leaded package type: a = 100-pin tqfp speed grade: 133 mhz v33 = 3.3 v process technology ? 90 nm part identifier: 146x = 1461 or 1463 1461 = ft, 1 mb 36 (36 mb) 1463 = ft, 2 mb 18 (36 mb) technology code: c = cmos marketing code: 7 = sram company id: cy = cypress 7 146x a - 133 x a v33 cy c x
cy7c1461av33 cy7c1463av33 document number: 38-05356 rev. *l page 19 of 24 package diagrams figure 7. 100-pin tqfp (14 20 1.4 mm) a100ra package outline, 51-85050 51-85050 *d
cy7c1461av33 cy7c1463av33 document number: 38-05356 rev. *l page 20 of 24 acronyms document conventions units of measure acronym description ce chip enable cen clock enable cmos complementary metal oxide semiconductor i/o input/output lsb least significant bit msb most significant bit nobl no bus latency oe output enable sram static random access memory tqfp thin quad flat pack ttl transistor-transistor logic we write enable symbol unit of measure c degree celsius mhz megahertz a microampere ma milliampere mv millivolt mm millimeter ms millisecond ns nanosecond ? ohm % percent pf picofarad vvolt wwatt
cy7c1461av33 cy7c1463av33 document number: 38-05356 rev. *l page 21 of 24 document history page document title: cy7c1461av33/cy7c1463av33, 36-mbit (1 m 36/2 m 18) flow-through s ram with nobl? architecture document number: 38-05356 revision ecn no. issue date orig. of change description of change ** 254911 see ecn syt new data sheet. part number changed from previous revision (new and old part number differ by the letter ?a?). *a 300131 see ecn syt updated features (removed 150 mhz and 117 mhz frequencies related information). updated selection guide (removed 150 mhz and 117 mhz frequencies related information). updated electrical characteristics (removed 150 mhz and 117 mhz frequencies related information). updated thermal resistance (replaced values of ? ja and ? jc parameters from tbd to 25.21 c/w and 2.58 c/w respectively for 100-pin tqfp package). updated switching characteristics (removed 150 mhz and 117 mhz frequencies related information). updated ordering information (added pb-free information for 100-pin tqfp, 165-ball fbga and 209-ball fbga pa ckages, added ?pb-free bg and bz packages availability? comment below the ordering information). *b 320813 see ecn syt updated pin configurations (changed h9 pin from v ssq to v ss for 209-ball fbga). updated electrical characteristics (changed the test condition for v ol parameter from v dd = min. to v dd = max., replaced the tbd?s with their respective values for i dd , i sb1 , i sb2 , i sb3 and i sb4 parameters). updated thermal resistance (replaced values of ? ja and ? jc parameters from tbd to respective thermal values for 165-ball fbga and 209-ball fbga packages). updated capacitance (changed values of c in , c clk and c i/o parameters to 6.5 pf, 3 pf and 5.5 pf from 5 pf, 5 pf and 7 pf for 100-pin tqfp package). updated ordering information (removed ?pb-free bg packages availability? comment below the ordering information). *c 331551 see ecn syt updated pin configurations (modified address expansion balls in the pinouts for 165-ball fbga and 209-ball fbga packages according to jedec standards). updated pin definitions . updated functional overview (updated zz mode electrical characteristics (changed maximum value of i ddzz parameter from tbd to 100 ma)). updated operating range (added industrial temperature range). updated electrical characteristics (updated test conditions for v ol and v oh parameters, changed maximum value of i sb2 parameter from 100 ma to 120 ma, changed maximum value of i sb4 parameter from 110 ma to 135 ma respectively). updated capacitance (changed values of c in , c clk and c i/o parameters to 7 pf, 7 pf and 6 pf from 5 pf, 5 pf and 7 pf for 165-ball fbga package). updated ordering information (by shading and unshading mpns according to availability).
cy7c1461av33 cy7c1463av33 document number: 38-05356 rev. *l page 22 of 24 *d 417547 see ecn rxu changed status from preliminary to final. changed address of cypress semicondu ctor corporation from ?3901 north first street? to ?198 champion court?. updated electrical characteristics (updated note 11 (changed test condition from v ih < v dd to v ih ?? v dd ), changed ?input load cu rrent except zz and mode? to ?input leakage current except zz and mode?, changed minimum value of i x parameter (corresponding to input current of mode (input = v ss )) from ?5 ? a to ?30 ? a, changed maximum value of i x parameter (corresponding to input current of mode (input = v dd )) from 30 ? a to 5 ? a respectively, changed minimum value of i x parameter (corresponding to input current of zz (input = v ss )) from ?30 ? a to ?5 ? a, changed maximum value of i x parameter (corresponding to input current of zz (input = v dd )) from 5 ? a to 30 ? a respectively). updated ordering information (updated part numbers, replaced package name column with package diagram in the ordering information table). updated package diagrams . *e 473650 see ecn vkn updated maximum ratings (added the maximum rating for supply voltage on v ddq relative to gnd). updated tap ac switching characteristics (changed minimum value of t th and t tl parameters from 25 ns to 20 ns, changed maximum value of t tdov parameter from 5 ns to 10 ns). updated ordering information (updated part numbers). *f 1274733 see ecn vkn / aesa updated switching waveforms (updated figure 5 (corrected typo)). *g 2499107 see ecn vkn / pyrs updated logic block diagram ? cy7c1465av33 (corrected typo). *h 2897278 03/22/2010 njy updated ordering information (removed obsolete part numbers). updated package diagrams . *i 3208774 03/29/2011 njy updated ordering information (updated part numbers) and added ordering code definitions . updated package diagrams . updated in new template. *j 3309506 07/12/2011 osn updated package diagrams . added acronyms and units of measure . document history page (continued) document title: cy7c1461av33/cy7c1463av33, 36-mbit (1 m 36/2 m 18) flow-through s ram with nobl? architecture document number: 38-05356 revision ecn no. issue date orig. of change description of change
cy7c1461av33 cy7c1463av33 document number: 38-05356 rev. *l page 23 of 24 *k 3591743 05/10/2012 njy / prit updated features (removed cy7c1465av33 related information, removed 165-ball fbga package, 209-ball fbga package related information). updated functional description (removed cy7c1465av33 related information, removed the note ?for best practices recomme ndations, refer to the cypress application note system design guidelines on www.cypress.com .? and its reference). updated selection guide (removed 100 mhz frequency related information). removed logic block diagram ? cy7c1465av33. updated pin configurations (removed 165-ball fbga package (corresponding to cy7c1461av33 and cy7c1463av33), 209-ball fbga package (corresponding to cy7c1465av33) related information). updated pin definitions (removed jtag related information). updated functional overview (removed cy7c1465av33 related information). updated truth table (removed cy7c1465av33 related information). removed truth table for read/write (corresponding to cy7c1465av33). removed ieee 1149.1 serial boundary scan (jtag). removed tap controller state diagram. removed tap controller block diagram. removed tap timing. removed tap ac switching characteristics. removed 3.3 v tap ac test conditions. removed 3.3 v tap ac output load equivalent. removed 2.5 v tap ac test conditions. removed 2.5 v tap ac output load equivalent. removed tap dc electrical charac teristics and operating conditions. removed identification register definitions. removed scan register sizes. removed identi fication codes. removed boundary scan order (corresponding to 165-ball fbga package). removed boundary scan order (corresponding to 209-ball fbga package). updated electrical characteristics (removed 100 mhz frequency related information). updated capacitance (removed 209-ball fbga package related information). updated thermal resistance (removed 209-ball fbga package related information). updated switching characteristics (removed 100 mhz frequency related information). updated package diagrams (removed 165-ball fbga package, 209-ball fbga package related information). replaced all instances of io with i/o across the document. *l 3690005 prit 07/24/2012 no technical updates. completing sunset review. document history page (continued) document title: cy7c1461av33/cy7c1463av33, 36-mbit (1 m 36/2 m 18) flow-through s ram with nobl? architecture document number: 38-05356 revision ecn no. issue date orig. of change description of change
document number: 38-05356 rev. *l revised july 24, 2012 page 24 of 24 nobl and no bus latency are trademarks of cypress semiconductor corporation. zbt is a trademark of integrated device technology , inc. all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c1461av33 cy7c1463av33 ? cypress semiconductor corporation, 2004-2012. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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